Part 2: Hardware Testing
Contents
Introduction
With total and precise control of the CLB layouts I was able to do some testing to do some ad-hoc characterization of the CLB module.
CLB Propagation Delay
I chained every CLB0-31 end to end as a buffer, with the input from a PPS input pin and the output going to a PPS output pin. I drove the PPS input pin from the MCU itself.
I could then measure the delay between a signal injected at the input and the output it was around 232ns for the rising edge and 211ns for the falling edge. We can then change the input of CLB31 to get it’s input from CLB29 (instead of CLB30) and measure the new delay (226ns/206ns). We can repeat this for every CLB until we are directly connected to the input.
With this data we can measure the incremental delay of every CLB element, here is a plot.
We can see some interesting things from this, the average propagation delays are:
- BLE31-25: Rising 5.43ns; Falling 4.61ns
- BLE23-17: Rising 5.52ns; Falling 4.48ns
- BLE15-9: Rising 6.04ns; Falling 5.46ns
- BLE1-7: Rising 6.36ns; Falling 5.77ns
Except at the boundaries i.e. BLE0/8/16/24 where we see bumps when we cross between banks of BLEs. If we use the average of the delays of the bank we can calculate the bank interconnect delay:
- Bank D to C: Rising 2.116ns; Falling 1.528ns
- Bank C to B; Rising 1.933ns; Falling 1.516ns
- Bank B to A; Rising 2.462ns; Falling 1.795ns
- Bank A to PPS: Rising 3.040ns; Falling 2.141ns
If we look at the spec from Microchip:
| Standard Operating Conditions (unless otherwise stated) | |||||
|---|---|---|---|---|---|
| Param No. | Sym. | Characteristic | Typ.† | Units | |
| CLB01* | TBLE | Single BLE input to output propagation time | 10 | ns | |
| CLB02* | TMIN_TRIG | Input minimum high to low time to trigger BLE | 5 | ns | |
| CLB02A* | Input minimum low to high time to trigger BLE | 8 | ns | ||
| CLB03* | TEC_SU | CLB Data Set-up time | 10 | ns | |
| CLB04* | TEC_H | CLB External Data Hold time | 10 | ns | |
| CLB05* | TEC_DC | CLB external clock duty cycle | 50 | % | |
| CLB06* | FMAX_SYNC | CLB module maximum clock frequency for synchronous applications | 16 | MHz | |
| CLB07* | FMAX_ASYNC | CLB module maximum switching frequency for asynchronous applications | 100 | MHz | |
| CLB08* | TCONFIG | CLB Configuration loading time MD = 01, Burst Mode |
206 | Cycles (TCY) | |
|
* These parameters are characterized but not tested. Min/Max values are not specified. † Typ. values at 3.0V, 25°C unless otherwise noted. Provided for design guidance only. |
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We can see they specd the Typ “Single BLE input to output propagation time” as 10ns this looks to be about double the value measured above. (It looks like this is actually the delay of a BLE plus the delay of the PPS interconnect.)
We can finally subtract the delay of the last BLE31, we can calculate the delay of the input/output PPS network as rising 35.613ns and falling 41.75ns (~19ns input and ~19ns output?).
CLB Delay Skew
This of course begs the question, how does the delay change across inputs to the CLB module itself?
If we set all the input MUXs to take an input form the same PPS input, then measure the delay skew as we change the inputs.
It’s actually remarkably flat the peaks at the transitions are not just between jumps they are all on the same playing field.
The first input on every LUT input just has a higher delay than the others.